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fractional-n / integer-n pll synthesizer preliminary technical data ADF4150 rev. pr i information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.46 1.3113 ? 2009 analog devices, inc. all rights reserved. features fractional-n synthesizer and integer-n synthesizer pro grammable divide-by-1/2/4/8 or 16 output 3.0 v to 3.6 v power supply 1.8 v logic compatibility separate charge pump supply (v p ) allows extended tuning voltage in 3 v systems programmable dual-modulus prescaler of 4/5 or 8/9 pro grammable output power level rf output mute function 3-wire serial interface analog and digital lock detect switched bandwidth fast-lock mode cycle slip reduction applications wireless infrastructure (wcdma, td-scdma, wimax, gsm, pcs , dcs, dect) test equipment wireless lans, catv equipment clock generation general description the ADF4150 allows implementation of fractionaln or in t egern phaselocked loop (pll) frequency synthesizers if used with an external voltage controlled oscillator (vco), loop filter and external reference frequency. the ADF4150 is for use with external vco parts and is software compatible with the adf4350. the vco frequency can be dividedby 1/2/4/8 or 16 to allow the user to generate rf output frequencies as low as 31.25 mhz. for applications that require isolation the rf output stage can be muted. the mute function is both pin and software controllable. control of all the onchip registers is through a simple 3wire interface. the device operates with a power supply ranging from 3.0 v to 3.6 v and can be powered down when not in use. the ADF4150 is available in a 4mm x 4mm package. functional block diagram muxout cp out ld sw ref in clk dat a le av dd sdv dd dv dd v p agnd ce dgnd cp gnd sd gnd r set rf out + rf out C rf in + rf in C phase comparator fl o switch char ge pump output stage rf input pdb rf m u l t ip l e x e r 10-bit r counter 2 divider 2 doubler function latch data register integer reg n counter fraction reg third-order fractional interpolator modulus reg multiplexer lock detect divide by 1/2/4/8/16 a d f 4150 figure 1.
preliminary technical data ADF4150 rev. pr i | page 2 of 27 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 specifications..................................................................................... 3 timing characteristics..................................................................... 5 absolute maximum ratings............................................................ 6 transistor count........................................................................... 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 9 circuit description......................................................................... 10 reference input section............................................................. 10 rf n divider............................................................................... 10 int, frac, mod and r counter relationship .................... 10 int n mode ............................................................................. 10 r counter .................................................................................... 10 phase frequency detector (pfd) and charge pump............ 10 muxout and lock detect................................................... 11 input shift registers................................................................... 11 program modes .......................................................................... 11 output stage................................................................................ 11 register maps .................................................................................. 12 register 0 ..................................................................................... 16 register 1 ..................................................................................... 16 register 2 ..................................................................................... 16 register 3 ..................................................................................... 17 register 4 ..................................................................................... 18 register 5 ..................................................................................... 18 initialization sequence .............................................................. 18 rf synthesizer a worked example ..................................... 19 modulus....................................................................................... 19 reference doubler and reference divider ............................. 19 12bit programmable modulus................................................ 19 cycle slip reduction for faster lock times........................... 20 spurious optimization and fast lock ...................................... 20 fastlock timer and register sequences ............................... 20 fast lockan example ............................................................ 20 fast lockloop filter topology............................................. 20 spur mechanisms ....................................................................... 21 spur consistency and fractional spur optimization ........... 21 phase resync............................................................................ 21 applications information .............................................................. 23 direct conversion modulator .................................................. 23 interfacing ................................................................................... 24 pcb design guidelines for chip scale package .................... 24 output matching ........................................................................ 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26
ADF4150 preliminary technical data rev. pri | page 3 of 27 specifications av dd = dv dd = sd vdd = 3.3 v 10%; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85c. table 1. parameter b v ersion unit conditions/comments ref in characteristics input frequency 10 to 250 mhz min to mhz max for f < 10 mhz ensure slew rate > 21 v/s input sensitivity 0.7 to av dd v p-p min to v p-p max biased at av dd /2 1 input capacitance 5.0 pf max input current 60 a max rf input characteristics rf input frequency (rf in ) 0.5/4.0 ghz min/max ?10 dbm/0 dbm minimum/maximum 4.0/6.0 ghz min/max ?5 dbm/0 dbm minimum/maximum for lower frequencies, ensure slew rate > 400 v/s phase detector phase detector frequency 2 32 mhz max charge pump i cp sink/source with r set = 5.1 k high value 5 ma typ low value 0.312 ma typ r set range 2.7 to 10 k min to k max sink and source current matching 2 % typ 0.5 v v cp v p - 0.5 v i cp vs. v cp 1.5 % typ 0.5 v v cp v p - 0.5 v i cp vs. temperature 2 % typ v cp = 2.0 v logic inputs input high voltage, v inh 1.5 v min input low voltage, v inl 0.6 v max input current, i inh /i inl 1 a max input capacitance, c in 3.0 pf max logic outputs output high voltage, v oh dv dd ? 0.4 v min cmos output chosen output high current, i oh 500 a max output low voltage, v o 0.4 v max i ol = 500 a power supplies av dd 3.0 to 3.6 v min to v max dv dd , sd vdd , av dd v p av dd /5.5 v min/v max di dd + ai dd 3 25 ma typ output dividers 6-24 ma typ each output divide by two consumes 6 ma i rfout 3 32 ma typ rf output stage is programmable low power sleep mode 7 a typ rf output characteristics minimum output frequency using rf output dividers 31.25 mhz 500 mhz vco input and divide by 16 selected maximum rf in frequency using rf output dividers 3500 mhz harmonic content (second) ?19 dbc typ fundamental vco output harmonic content (third) - 13 dbc typ fundamental vco output harmonic content (second) ?20 dbc typ divided vco output harmonic content (third) - 10 dbc typ divided vco output output power 4 ?4 to +5 dbm typ min to dbm typ max programmable in 3 db steps output power variation 1 db typ
preliminary technical data ADF4150 rev. pri | page 4 of 27 parameter b version unit conditions/comments noise characteristics normalized in-band phase noise floor 5 ?219 dbc/hz typ anti-backlash pulse width set to 6 ns. normalized in-band phase noise floor 6 ?222 dbc/hz typ anti-backlash pulse width set to 3 ns. spurious signals due to pfd frequency ?70 dbc typ level of signal with rf mute enabled ?40 dbm typ 1 ac coupling ensures av dd /2 bias. 2 guaranteed by design. sample tested to ensure compliance. 3 t a = 25c; av dd = dv dd = 3.3 v; prescaler = 8/9; f refin = 100 mhz; f pfd = 25 mhz; f rf = 2.5 ghz. 4 using 50 resistors to v vco , into a 50 load. 5 this figure can be used to calculate phase noise for any application. to calculate in-band phase noise performance as seen at the vco output use the following formula: ?213 + 10l og(f pfd ) + 20 logn . the value given is the lowest noise mode. f refin = 100 mhz; f pfd = 25 mhz; offset frequency = 50 khz; vco frequency = 1850.1 mhz. n = 74; loop bw = 500 khz, i cp = 2.5 ma; low noise mode. the noise was measured with an eval-ADF4150eb1z and the agilent e5052a signal source analyzer. 6 this figure can be used to calculate phase noise for any application. to calculate in-band phase noise performance as seen at the vco output use the following formula: ?213 + 10l og(f pfd ) + 20 logn . the value given is the lowest noise mode. f refin = 100 mhz; f pfd = 25 mhz; offset frequency = 50 khz; vco frequency = 1850 mhz. n = 74; loop bw = 500 khz, i cp = 2.5 ma; low noise mode. the noise was measured with an eval-ADF4150eb1z and the agilent e5052a signal source analyzer.
ADF4150 preliminary technical data rev. pri | page 5 of 27 timing characteristics av dd = dv dd = sd vdd = 3.3 v 10%; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85c. table 2. parameter limit (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le setup time t 7 20 ns min le pulse width clock data le le db31 (msb) db30 db1 (control bit c2) db2 (control bit c3) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 07325-002

ADF4150 preliminary technical data rev. pri | page 6 of 27 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rat ing av dd to gnd 1 ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v p to av dd ?0.3 v to +5.8 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v dd + 0.3 v ref in to gnd ?0.3 v to v dd + 0.3 v operating temperature range ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c lfcsp ja thermal impedance 27.3c/w (paddle-soldered) reflow soldering peak temperature 260c time at peak temperature 40 sec 1 gnd = agnd = dgnd = 0 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. transistor count 23380 (cmos) and 809 (bipolar) esd caution
preliminary technical data ADF4150 rev. pri | page 7 of 27 pin configuration and function descriptions pin 1 indicator 1clk 2da ta 3le 4ce 5sw 6v p 15 16 17 1 8 1 4 13 agnd 7 c p 8 c p g n d 9 1 1 1 2 a g n d 1 0 2 1 m u x o u t 2 2 2 3 2 4 2 0 l d 1 9 top view ADF4150 rf in + rf in ? rf out + rf o ut ? ref in pdb rf d v d d s d v d d s d g n d r set av dd 1 av dd 2 figure 3. pin configuration, 24 lead 4mm x 4 mm table 4. pin function descriptions pin no. m nemonic function 1 clk serial clock input. data is clocked into the 32-bit shift register on the clk rising edge. this input is a high impedance cmos input. 2 data serial data input. the serial data is loaded msb first with the three lsbs as the control bits. this input is a high impedance cmos input. 3 le load enable, cmos input. when le goes high, the data stored in the shift register is loaded into the register that is selected by the three lsbs. 4 ce chip enable. a logic low on this pin powers down the device and puts the charge pump into three-state mode. taking the pin high powers up the device depending on the status of the power-down bits. 5 sw fastlock switch. a connection should be made from the loop filter to this pin when using the fastlock mode. 6 v p charge pump power supply. this should be greater than or equal to av dd . in systems where av dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5.5 v. 7 cp charge pump output. when enabled, this provides i cp to the external loop filter. the output of the loop filter is connected to v tune to drive the external vco. 8 cp gnd charge pump ground. this is the ground return pin for cp out . 9 av dd 1 analog power supply. this ranges from 3.0 v to 3.6 v. decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. av dd must have the same value as dv dd . 10 rf in + input to the rf input. this small signal input is ac-coupled to the external vco. 11 rf in ? complementary input to the rf input. this point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. 12,13 a gnd analog ground. this is a ground return pin for av dd 1 and av dd 2. 14 rf out ? complementary rf output. the output level is programmable. the vco fundamental output or a divided down version is available. 15 rf out + rf output. the output level is programmable. the vco fundamental output or a divided down version is available. 16 av dd 2 analog power supply. this ranges from 3.0 v to 3.6 v. decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. av dd 2 must have the same value as dv dd . 17 pdb rf rf power-down. a logic low on this pin mutes the rf outputs. this function is also software controllable. 18 dv dd digital power supply. should be the same voltage as av dd . decoupling capacitors to the ground plane should be placed as close as possible to this pin. 19 ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k. this input can be driven from a ttl or cmos crystal oscillator, or it can be ac-coupled. 20 ld lock detect output pin. this pin outputs a logic high to indicate pll lock. a logic low output indicates loss of pll lock. 21 muxout multiplexer output. this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally.
ADF4150 preliminary technical data rev. pri | page 8 of 27 pin no. mnemonic function 22 sdv dd power supply pin for the digital -? modulator. should be the same voltage as av dd . decoupling capacitors to the ground plane are to be placed as close as possible to this pin. 23 sd gnd digital -? modulator ground. ground return path for the -? modulator. 24 r set connecting a resistor between this pin and gnd sets the charge pump output current. the nominal voltage bias at the r set pin is 0.55 v. the relationship between i cp and r set is set cp r 25. 5 i = whe re r set = 5.1 k, i cp = 5 ma.
preliminary technical data ADF4150 rev. pri | page 9 of 27 typical performance characteristics tbd all caps (initial cap) all caps (initial cap) C0000 C0000 C 0000 C0000 C0000 C000 C000 C000 C000 C000 00000-0-000 tbd all caps (initial cap) all caps (initial cap) C0000 C0000 C 0000 C0000 C0000 C000 C000 C000 C000 C000 00000-0-000 figure 4 figure 5. tbd all caps (initial cap) all caps (initial cap) C0000 C0000 C 0000 C0000 C0000 C000 C000 C000 C000 C000 00000-0-000 tbd all caps (initial cap) all caps (initial cap) C0000 C0000 C 0000 C0000 C0000 C000 C000 C000 C000 C000 00000-0-000 figure 6. figure 7. tbd all caps (initial cap) all caps (initial cap) C0000 C0000 C 0000 C0000 C0000 C000 C000 C000 C000 C000 00000-0-000 tbd all caps (initial cap) all caps (initial cap) C0000 C0000 C 0000 C0000 C0000 C000 C000 C000 C000 C000 00000-0-000 figure 8. fig ure 9.
ADF4150 preliminary technical data rev. pri | page 10 of 27 circuit description reference input section the reference input stage is shown in figure 5. sw1 and sw2 are normally closed switches. sw3 is normally open. when powerdown is initiated, sw3 is closed, and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on powerdown. 07325-005 buffer to r counter ref in 100k nc sw2 sw3 no nc sw1 power-down control figure 10. reference input stage rf n divider the rf n divider allows a division ratio in the pll feedback pat h. division ratio is determined int, frac and mod values, which build up this divider. int, frac, mod and r counter relationship the int, frac, and mod values, in conjunction with the r cou nter, make it possible to generate output frequencies that are spaced by fractions of the pfd frequency. see the rf synthesizera worked example section for more information. the rf vco frequency (rf out ) equation is rf out = f pfd ( int + ( frac / mod )) (1) where rf out is the output frequency of external voltage controlled oscillator (vco). f pfd = ref in [(1 + d )/( r (1 + t ))] (2) where ref in is the reference input frequency. d is the ref in doubler bit. t is the ref in divideby2 bit (0 or 1). r is the preset divide ratio of the binary 10Cbit programmable reference counter (1 to 1023). int is the preset divide ratio of the binary 16Cbit counter (23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler). mod is the preset fractional modulus (2 to 4095). frac is the numerator of the fractional division (0 to mod ? 1). third order fractional interpolator frac value mod reg int reg rf n divider n = int + frac/mod from vco output/ output dividers to pfd n counter 07325-006 figure 11. rf int divider int n mode if the frac = 0 and db8 in register 2 (ldf) is set to 1, the syn thesizer operates in integern mode. the db8 in register 2 (ldf) should be set to 1 to get integern digital lock detect. r counter the 10Cbit r counter allows the input reference frequency (re f in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 1023 are allowed. phase frequency detector (pfd) and cha rge pump the phase frequency detector (pfd) takes inputs from the r cou nter and n counter and produces an output proportional to the phase and frequency difference between them. figure 12 is a simplified schematic of the phase frequency detector. the pfd includes a programmable delay element that sets the width of the antibacklash pulse, which can be either 6 ns (default) or 3 ns (for integern mode). this pulse ensures there is no dead zone in the pfd transfer function, and gives a consistent reference spur level. u3 clr2 q2d2 u2 down up hi hi cp Cin +in charge pump d elay clr1 q1d1 u1 07325-007 figure 12. pfd simplified schematic
preliminary technical data ADF4150 rev. pr i | page 11 of 27 muxout and lock detect the output multiplexer on the ADF4150 allows the user to acc ess various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 (for details, see figure 18). figure 13 shows the muxout section in block diagram form. 07325-008 d gnd dv dd control mux mux out analog lock detect digital lock detect r counter output n counter output d gnd reserved three-state-output dv dd figure 13. muxout schematic input shift registers the ADF4150 digital section includes a 10Cbit rf r counter, a 1 6Cbit rf n counter, a 12bit frac counter, and a 12Cbit modulus counter. data is clocked into the 32Cbit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of six latches on the rising edge of le. the destination latch is determined by the state of the three control bits (c3, c2 and c1) in the shift register. these are the 3 lsbs, db2, db1, and db0, as shown in figure 2. the truth table for these bits is shown in table 5. figure 19 shows a summary of how the latches are programmed. program modes table 5 and figure 11 through figure 21 show how the program mo d es are to be set up in the ADF4150. a number of settings in the ADF4150 are double buffered. these include the modulus value, phase value, r counter value, reference doubler, reference divideby2, and current setting. this means that two events have to occur before the part uses a new value of any of the double buffered settings. first, the new value is latched into the device by writing to the appropriate register. second, a new write must be performed on register r0. for example, any time the modulus value is updated, register 0 (r0) must be written to, to ensure the modulus value is loaded correctly. divider select in register 4 (r4) is also double buffered, but only if db13 of register 2 (r2) is high. table 5. c3, c2 and c1 truth table control bits c3 c2 c1 register 0 0 0 register 0 (r0) 0 0 1 register 1 (r1) 0 1 0 register 2 (r2) 0 1 1 register 3 (r3) 1 0 0 register 4 (r4) 1 0 1 register 5 (r5) output stage the rf out + and rf out pins of the ADF4150 family are connected to the collectors of an npn differential pair driven by buffered outputs of the vco, as shown in figure 14. to allow the user to optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable by bit d2 and bit d1 in register 4 (r4). four current levels may be set. these levels give output power levels of ?4 dbm, ?1 dbm, +2 dbm, and +5 dbm, respectively, using a 50 resistor to vdd and ac coupling into a 50 load. alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180 microstrip coupler (see output matching section)if the outputs are used individually, the optimum output stage consists of a shunt inductor to vdd. another feature of the ADF4150 family is that the supply current to the rf output stage can be shut down until the part achieves lock as measured by the digital lock detect circuitry. this is enabled by the mutetilllock detect (mtld) bit in register 4 (r4). mux rf out + r f out - buffer/ d ivide-by 1/2/4/8/16 07325-010 figure 14. output stage
ADF4150 preliminary technical data rev. pri | page 12 of 27 register maps 07325-011 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 p1 p12 p11 p10 p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 d1 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(0) c2(1) c1(0) csr rdiv2 reference doubler current setting 10-bit r counter control bits db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 f3 f2 v2 v1 f1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value ldp pd polarity pd cp three- state counter reset output power clk div mode dbr 1 1 dbr = double buffered registerbuffered by the write to register 0. 2 dbb = double buffered bitsbuffered by the write to register 0, if and only if db13 of register 2 is high. reserved ldf reserved register 4 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d13 d12 d11 d10 0 0 0 0 0 0 0 0 0 d8 d7 d6 d5 d4 d3 d2 d1 c3(1) c2(0) c1(0) control bits rf output enable ld pin mode mtld divider select feedback select register 0 register 1 re gister 2 register 3 register 5 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d15 d14 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(1) control bits reserved reserved dbb 2 double buff reserved reserved dbr 1 dbr 1 dbr 1 dbr 1 dbr 1 reserved reserved reserved prescaler noise mode muxout reserved reserved reserved charge cancel abp figure 15. register summary
preliminary technical data ADF4150 rev. pr i | page 13 of 27 07325-012 n16 n15 ... n5 n4 n3 n2 n1 integer value (int) 0 0 ... 0 0 0 0 0 not allowed 0 0 ... 0 0 0 0 1 not allowed 0 0 ... 0 0 0 1 0 not allowed . . ... . . . . . ... 0 0 ... 1 0 1 1 0 not allowed 0 0 ... 1 0 1 1 1 23 0 0 ... 1 1 0 0 0 24 . . ... . . . . . ... 1 1 ... 1 1 1 0 1 65533 1 1 ... 1 1 1 1 0 65534 1 1 ... 1 1 1 1 1 65535 f12 f11 .......... f2 f1 fractional value (frac) 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 ......... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) intmin = 75 with prescaler = 8/9 figure 16. register 0 (r0) 07325-013 p12 p11 .......... p2 p1 phase value (phase) 0 0 .......... 0 0 0 0 0 .......... 0 1 1 (recommended) 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 p1 p12 p11 p10 p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) reserved m12 m11 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... m2 m1 interpolator modulus (mod) 0 0 1 0 2 0 0 1 1 3 . . . . . . . . . . . . . . . 1 1 0 0 4092 1 1 0 1 4093 1 1 1 0 4094 1 1 1 1 4095 prescaler p1 prescaler 0 4/5 1 8/9 figure 17. register 1 (r1)
ADF4150 preliminary technical data rev. pr i | page 14 of 27 07325-014 rd2 reference doubler 0 disabled 1 enabled rd1 reference divide by 2 0 disabled 1 enabled cp4 cp3 cp2 cp1 i cp (ma) 5.1k 0 0 0 0 0.31 0 0 0 1 0.63 0 0 1 0 0.94 0 0 1 1 1.25 0 1 0 0 1.56 0 1 0 1 1.88 0 1 1 0 2.19 0 1 1 1 2.50 1 0 0 0 2.81 1 0 0 1 3.13 1 0 1 0 3.44 1 0 1 1 3.75 1 1 0 0 4.06 1 1 0 1 4.38 1 1 1 0 4.69 1 1 1 1 5.00 r10 r9 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... r2 r1 r divider (r) 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 1020 1 1 0 1 1021 1 1 1 0 1022 1 1 1 1 1023 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 d1 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(0) c2(1) c1(0) rdiv2 reference doubler current setting 10-bit r counter control bits ldp pd polarity pd cp three- state counter reset ldf muxout double buff u5 ldp 0 10ns 1 6ns u4 pd polarity 0 negative 1 positive u3 power down 0 disabled 1 enabled u2 cp three-state 0 disabled 1 enabled u1 counter reset 0 disabled 1 enabled d1 doublebuffer r4 db22-20 0 disabled 1 enabled u6 ldf 0 frac-n 1 int-n reserved noise mode m3 m2 m1 output 0 0 0 three-state output 0 0 1 dv dd 0 1 0 dgnd 0 1 1 r divider output 1 0 0 n divider output 1 0 1 analog lock detect 1 1 0 digital lock detect 1 1 1 reserved l1 l2 noise mode 0 0 low noise mode 0 1 reserved 1 0 reserved 1 1 low spur mode figure 18. register 2 (r2) 07325-015 c2 c1 clock divider mode 0 0 clock divider off 0 1 fastlock enable 1 0 resync enable 1 1 reserved d12 d11 .......... d2 d1 clock divider value 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 csr db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 f3 f2 f1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value clk div mode reserved f1 cycle slip reduction 0 disabled 1 enabled reserved 0 0 reserved f2 charge cancellation 0 disabled 1 enabled f3 anti-backlash pulse width 0 6 ns (frac-n) 1 3 ns (int_n) charge cancel abp figure 19. register 3 (r3)
preliminary technical data ADF4150 rev. p r i | page 15 of 27 07325-016 d3 rf out 0 disabled 1 enabled output power db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d13 d12 d11 d10 0 0 0 0 0 0 0 0 0 d8 0 0 0 0 d3 d2 d1 c3(1) c2(0) c1(0) control bits reserved rf output enable mtld output divider select feedback select reserved d2 d1 output power 0 0 -4 0 1 -1 1 0 +2 1 1 +5 d8 mute till lock detect 0 mute disabled 1 mute enabled d12 d11 rf divider select 0 0 /1 0 0 /2 0 1 /4 0 1 /8 d10 0 1 0 1 1 0 /16 0 d13 feedback select 0 fundamental 1 divided reserved figure 20. register 4 (r4) 07325-017 ld pin mode db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d15 d14 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(1) control bits reserved reserved reserved d1 5 d1 4 lock detect pin operation 0 0 low 0 1 digital lock detect 1 0 low 1 1 high reserved figure 21. register 5 (r5)
ADF4150 preliminary technical data rev. pri | page 16 of 27 register 0 control bits with bits [c3:c1] set to 0, 0, 0, register 0 is programmed. figu re 16 shows the input data format for programming this register. 16-bit int value these sixteen bits set the int value, which determines the int eger part of the feedback division factor. it is used in equation 1 (see the int, frac, mod and r counter relationship section). all integer values from 23 to 65,535 are allowed for 4/5 prescaler. for 8/9 prescaler, the minimum integer value is 75. 12-bit frac value the 12 frac bits set the numerator of the fraction that is input to the ? modulator. this, along with int, specifies the new frequency channel that the synthesizer locks to, as shown in the rf synthesizera worked example section. frac values from 0 to mod ? 1 cover channels over a frequency range equal to the pfd reference frequency. register 1 control bits with bits [c3:c1] set to 0, 0, 1, register 1 is programmed. figu re 17 shows the input data format for programming this register. prescaler value the dual modulus prescaler (p/p + 1), along with the int, fra c, and mod counters, determines the overall division ratio from the vco output to the pfd input. operating at cml levels, it takes the clock from the vco output and divides it down for the counters. it is based on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 3 ghz. therefore, when operating the ADF4150 above 3 ghz, this must be set to 8/9. the prescaler limits the int value, where: p = 4/5, n min = 23 p = 8/9, n min = 75 in the ADF4150 p1 in register 1 sets the prescaler values. 12-bit phase value these bits control what is loaded as the phase word. the word mu s t be less than the mod value programmed in register 1. the word is used to program the rf output phase from 0 to 360 with a resolution of 360/mod. see the phase resync section for more information. in most applications, the phase relationship between the rf signal and the reference is not important. in such applications, the phase value can be used to optimize the fractional and subfractional spur levels. see the spur consistency and fractional spur optimization section for more information. if neither the phase resync nor the spurious optimization functions are being used, it is recommended the phase word be set to 1. 12-bit interpolator mod value this programmable register sets the fractional modulus. this is the ratio of the pfd frequency to the channel step resolution on the rf output. please refer to the rf synthesizera worked example section for more information. register 2 control bits with bits [c3:c1] set to 0, 1, 0, register 2 is programmed. figu re 18 shows the input data format for programming this register. noise and spur modes the noise modes on the ADF4150 are controlled by db30 and db2 9 in register 2 (see figure 18). the noise modes allow the user to optimize a design either for improved spurious performance or for improved phase noise performance. when the lowest spur setting is chosen, dither is enabled. this randomizes the fractional quantization noise so it resembles white noise rather than spurious noise. as a result, the part is optimized for improved spurious performance. this operation would normally be used when the pll closedloop bandwidth is wide, for fastlocking applications. (wide loop bandwidth is seen as a loop bandwidth greater than 1/10 of the rf out channel step resolution (f res )). a wide loop filter does not attenuate the spurs to the same level as a narrow loop bandwidth. for best noise performance, use the lowest noise setting option. as well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance. this setting is extremely useful where a narrow loop filter band width is available. the synthesizer ensures extremely low noise and the filter attenuates the spurs. the typical performance characteristics give the user an idea of the tradeoff in a typical wcdma setup for the different noise and spur settings.
preliminary technical data ADF4150 rev. pri | page 17 of 27 muxout the onchip multiplexer is controlled by bits [db28:db26](see figu re 18). reference doubler setting db25 to 0 feeds the ref in signal directly to the 10Cbit r counter, disabling the doubler. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 10Cbit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and the lowest spur mode is chosen, the inband phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for the ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cycle in the lowest noise mode. the phase noise is insensitive to ref in duty cycle when the doubler is disabled. the maximum allowable ref in frequency when the doubler is enabled is 30 mhz. rdiv2 setting the db24 bit to 1 inserts a divideby2 toggle flipflop bet ween the r counter and pfd, which extends the maximum ref in input rate. this function allows a 50% duty cycle signal to appear at the pfd input, which is necessary for cycle slip reduction. 10Cbit r counter the 10Cbit r counter allows the input reference frequency (r e f in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 1023 are allowed. double buffer db13 enables or disables double buffering of bits [db22:db20] in r egister 4. the divider select section explains how double buffering works. charge pump current setting bits [db12:db09] set the charge pump current setting. this shou ld be set to the charge pump current that the loop filter is designed with (see figure 18). ldf setting db8 to 1 enables integerCn digital lock detect, when fra c part of the divider is zero; setting db8 to 0 enables fractionalCn digital lock detect. lock detect precision (ldp) when db7 is set to 0, 40 consecutive pfd cycles of 10 ns must oc c ur before digital lock detect is set. when this bit is programmed to 1, 40 consecutive reference cycles of 6 ns must occur before digital lock detect is set. when db8 is set to 0, the fractionaln digital lock detect is activated. when db8 is set to 1, the integerCn digital lock detect is activated. in this case, setting db7 to 0 causes three consecutive cycles of 15 ns to occur before digital lock detect is set. when this bit is set to 1, five consecutive cycles of 15 ns must occur. phase detector polarity db6 sets the phase detector polarity. when a passive loop filter, or noninverting active loop filter us used, this should be set to 1. if an active filter with an inverting characteristic is used, it should be set to 0. power-down db5 provides the programmable powerdown mode. setting this bit to 1 performs a powerdown. setting this bit to 0 returns the synthesizer to normal operation. when in software powerdown mode, the part retains all information in its registers. only if the supply voltages are removed are the register contents lost. when a powerdown is activated, the following events occur: the synthesizer counters are forced to their load state conditions. the charge pump is forced into threestate mode. the digital lock detect circuitry is reset. the rf out buffers are disabled. the input register remains active and capable of loading and latching data. charge pump three-state db4 puts the charge pump into threestate mode when pr o grammed to 1. it should be set to 0 for normal operation. counter reset db3 is the r counter and n counter reset bit for the ADF4150. when this is 1, the rf synthesizer n counter and r counter are held in reset. for normal operation, this bit should be set to 0. register 3 control bits with bits [c3:c1] set to 0, 1, 1, register 3 is programmed. figu re 19 shows the input data format for programming this register.
ADF4150 preliminary technical data rev. pri | page 18 of 27 anti-backlash pulse width setting db22 bit to 0 sets the pfd antibacklash pulse width to 6 n s. this is the recommended mode for fractionaln use. setting this bit to 1, the 3 ns pulsewidth is used and will result in a phase noise and spur improvement in integern operation. for fractionaln mode it is not recommended to use this smaller setting. charge cancellation mode pulse width setting this bit to 1 enables charge pump charge cancellation. thi s has the effect of reducing pfd spurs in integern mode. in fractionaln mode this should not be used and the relevant result in a phase noise and spur improvement. for fractionaln mode it is not recommended to use this smaller setting. csr enable setting this bit to 1 enables cycle slip reduction. this is a met hod for improving lock times. note that the signal at the phase frequency detector (pfd) must have a 50% duty cycle for cycle slip reduction to work. the charge pump current setting must also be set to a minimum. see the cycle slip reduction for faster lock time section for more information. clock divider mode bits [db16:db15] must be set to 1, 0 to activate phase resync or 0, 1 to activate fast lock. setting bits [db16:db15] to 0, 0 disables the clock divider. see figure 19. 12-bit clock divider value the 12bit clock divider value sets the timeout counter for act ivation of phase resync. see the phase resync section for more information. it also sets the timeout counter for fast lock. see the fastlock timer and register sequences section for more information. register 4 control bits with bits [c3: c1] set to 1, 0, 0, register 4 is programmed. fi gu re 20 shows the input data format for programming this register. feedback select db23 selects the feedback from vco output to the ncounter. whe n set to 1, the signal is taken from the vco directly. when set to 0, it is taken from the output of the output dividers. the dividers enable covering of the wide frequency band (137.5 mhz C 4.4 ghz). when the divider is enabled and the feedback signal is taken from the output, the rf output signals of two separately configured plls are in phase. this is useful in some applications where the positive interference of signals is required to increase the power. div ider select bits [db22:db20] select the value of the output divider (see fi gu re 20). mute-till-lock detect if db10 is set to 1, the supply current to the rf output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. rf output enable db5 enables or disables primary rf output, depending on the chos en value. out put power db4 and db3 set the value of the primary rf output power le v el (see figure 20). register 5 control bits with bits [c3:c1] set to 1, 0, 1, register 5 is programmed. figu re 21 shows the input data form for programming this register. lock detect pin operation bits [db32:db22] set the operation of the lock detect pin (see figu re 21). initialization sequence the following sequence of registers is the correct sequence for ini tial power up of the ADF4150 after the correct application of voltages to the supply pins: register 5 register 4 register 3 register 2 register 1 register 0
preliminary technical data ADF4150 rev. pr i | page 19 of 27 rf synthesizer a worked example the following is an example how to program the ADF4150 syn thesizer: rf out = [int + (frac/mod)] [f pfd ]/rfdivider (3) where: rf ou t is the rf frequency output. int is the integer division factor. frac is the fractionality. mod is the modulus. rf divider is the output divider that divides down the vco fr e quency. f pfd = ref in [(1 + d) /( r (1 +t ))] (4) where: ref in is the reference frequency input. d is the rf ref in doubler bit. t is the reference divideby2 bit (0 or 1). r is the rf reference division factor. for example, in a umts system, where 2112.6 mhz rf frequency output (rf out ) is required, a 10 mhz reference frequency input (ref in ) is available, and a 200 khz channel resolution (f resout ) is required, on the rf output. a 2.1 ghz vco would be suitable, but a 4.2 ghz vco would be suitable also. in the second case, the rf divider of 2 should be used (vco frequency = 4225.2 mhz, rf out = vco frequency/rf divider = 4225.2 mhz/2 = 2112.6 mhz). it is also important where the loop is closed. in this example the loop is closed as depicted in figure 18 (from out divider). f pfd pfd vco n divider 2 07325-027 rf out
1$"-2$' 200 khz channel resolution (f resout ) is required at the output of the rf divider. therefore, channel resolution at the output of the vco ( f res ) is to be twice the f resout , that is 400khz. mod = ref in / f res mod = 10 mhz/400 khz = 25 from equation 4 f pfd = [10 mhz (1 + 0)/1] = 10 mhz (5) 2112.6 mhz = 10 mhz ( int + frac /25)/2 (6) where: int = 422 frac = 13 modulus the choice of modulus (mod) depends on the reference signal (r e f in ) available and the channel resolution (f res ) required at the rf output. for example, a gsm system with 13 mhz ref in sets the modulus to 65. this means the rf output resolution (f res ) is the 200 khz (13 mhz/65) necessary for gsm. with dither off, the fractional spur interval depends on the modulus values chosen (see table 6). reference doubler and reference divider the reference doubler onchip allows the input reference signal t o be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually improves noise performance by 3 db. it is important to note that the pfd cannot operate above 32 mhz due to a limitation in the speed of the ? circuit of the ndivider. the reference divideby2 divides the reference signal by 2, resulting in a 50% duty cycle pfd frequency. this is necessary for the correct operation of the cycle slip reduction (csr) function. see the cycle slip reduction for faster lock times section for more information. 12-bit programmable modulus unlike most other fractionaln plls, the ADF4150 allows the us e r to program the modulus over a 12Cbit range. this means the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 10Cbit r counter. for example, consider an application that requires 1.75 ghz rf and 200 khz channel step resolution. the system has a 13 mhz reference signal. one possible setup is feeding the 13 mhz directly to the pfd and programming the modulus to divide by 65. this results in the required 200 khz resolution. another possible setup is using the reference doubler to create 26 mhz from the 13 mhz input signal. this 26 mhz is then fed into the pfd programming the modulus to divide by 130. this also results in 200 khz resolution and offers superior phase noise performance over the previous setup. the programmable modulus is also very useful for multi standard applications. if a dualmode phone requires pdc and gsm 1800 standards, the programmable modulus is a great benefit. pdc requires 25 khz channel step resolution, whereas gsm 1800 requires 200 khz channel step resolution. a 13 mhz reference signal can be fed directly to the pfd, and the modulus can be programmed to 520 when in pdc mode (13 mhz/520 = 25 khz). the modulus needs to be reprogrammed to 65 for gsm 1800 operation (13 mhz/65 = 200 khz). it is important that the pfd frequency remain constant (13 mhz). this allows the user to design one loop filter for both setups without running into stability issues. it is important to remember that the ratio of the rf frequency to the pfd frequency principally affects the loop filter design, not the actual channel spacing.
ADF4150 preliminary technical data rev. pr i | page 20 of 27 cycle slip reduction for faster lock times as outlined in the noise and spur mode section, the ADF4150 con tains a number of features that allow optimization for noise performance. however, in fast locking applications, the loop bandwidth generally needs to be wide, and therefore, the filter does not provide much attenuation of the spurs. if the cycle slip reduction feature is enabled, the narrow loop bandwidth is maintained for spur attenuation but faster lock times are still possible. cycle slips cycle slips occur in integern/fractionaln synthesizers when the loop bandwidth is narrow compared to the pfd frequency. the phase error at the pfd inputs accumulates too fast for the pll to correct, and the charge pump temporarily pumps in the wrong direction. this slows down the lock time dramatically. the ADF4150 contains a cycle slip reduction feature that extends the linear range of the pfd, allowing faster lock times without modifications to the loop filter circuitry. when the circuitry detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. this outputs a constant current to the loop filter, or removes a constant current from the loop filter (depending on whether the vco tuning voltage needs to increase or decrease to acquire the new frequency). the effect is that the linear range of the pfd is increased. loop stability is maintained because the current is constant and is not a pulsed current. if the phase error increases again to a point where another cycle slip is likely, the ADF4150 turns on another charge pump cell. this continues until the ADF4150 detects the vco frequency has gone past the desired frequency. the extra charge pump cells are turned off one by one until all the extra charge pump cells have been disabled and the frequency is settled with the original loop filter bandwidth. up to seven extra charge pump cells can be turned on. in most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times. setting bit db18 in the register 3 to 1 enables cycle slip reduction. note that the pfd requires a 45% to 55% duty cycle for csr to operate correctly. spurious optimization and fast lock narrow loop bandwidths can filter unwanted spurious signals, bu t these usually have a long lock time. a wider loop bandwidth will achieve faster lock times, but a wider loop bandwidth may lead to increased spurious signals inside the loop bandwidth. the fast lock feature can achieve the same fast lock time as the wider bandwidth, but with the advantage of a narrow final loop bandwidth to keep spurs low. fast-lock timer and register sequences if the fastlock mode is used, a timer value is to be loaded into the pll to determine the duration of the wide bandwidth mode. when bits [db16:db15] in register 3 are set to 0, 1 (fast lock enable), the timer value is loaded by the 12Cbit clock divider value. the following sequence must be programmed to use fast lock: 1) initialization sequence (see the initialization sequence section); occurs only once after powering up the part. 2) load register 3 by setting bits [db16:db15] to 0, 1 and the chosen fastlock timer value [db14:db3]. note that the duration the pll remains in wide bandwidth is equal to the fastlock timer/f pfd . fast lockan example if a pll has reference frequencies of 13 mhz and f pfd = 13 mhz and a required lock time of 50 s, the pll is set to wide bandwidth for 40 s. this example assumes a modulus of 65 for channel spacing of 200 khz. if the time period set for the wide bandwidth is 40 s, then fast-lock timer value = time in wide bandwidth f pfd / mod fast-lock timer value = 40 s 13 mhz / 65 = 8 therefore, 8 must be loaded into the clock divider value in register 3 in step 1 of the sequence described in the fastlock timer and register sequences section. fast lockloop filter topology in order to use fastlock mode, the damping resistor in the loop fi l ter is reduced to ? of its value while in wide bandwidth mode. to achieve the wider loop filter bandwidth, the charge pump current increases by a factor of 16, and to maintain loop stability the damping resistor must be reduced a factor of ?. to enable fast lock, the sw pin is shorted to the gnd pin by settings bits [db16:db15] in register 3 to 0, 1. the following two topologies are available: the damping resistor (r1) is divided into two values (r1 and r1a) that have a ratio of 1:3 (see figure 23). an extra resistor (r1a) is connected directly from sw, as shown in figure 24. the extra resistor is calculated such that the parallel combination of an extra resistor and the damping resistor (r1) is reduced to ? of the original value of r1 (see figure 24).
preliminary technical data ADF4150 rev. pri | page 21 of 27 ADF4150 cp sw c1 c 2 r2 r1 r1a c3 vco 07325-018 figure 23. fast-lock loop filter topologytopology 1 ADF4150 cp sw c1 c2 r2 r1 r1a c3 vco 07325-019 figure 24. fast-lock loop filter topologytopology 2 spur mechanisms this section describes the three different spur mechanisms that ari se with a fractionaln synthesizer and how to minimize them in the ADF4150. fractional spurs the fractional interpolator in the ADF4150 is a third order ? mod ulator (sdm) with a modulus (mod) that is programmable to any integer value from 2 to 4095. in low spur mode (dither enabled) the minimum allowable value of mod is 50 . the sdm is clocked at the pfd reference rate (f pfd ) that allows pll output frequencies to be synthesized at a channel step resolution of f pfd /mod. in low noise mode (dither off), the quantization noise from the ? modulator appears as fractional spurs. the interval between spurs is f pfd /l, where l is the repeat length of the code sequence in the digital ? modulator. for the thirdorder modulator used in the ADF4150, the repeat length depends on the value of mod, as listed in table 6. theadd4dwftimlpoted(rsftdplmkdnlmkafdl))dd condition (dither off) rep eat length spur interval if mod is divisible by 2, but not 3 2 mod channel step/2 if mod is divisible by 3, but not 2 3 mod channel step/3 if mod is divisible by 6 6 mod channel step/6 otherwise mod channel step in low spur mode (dither enabled), the repeat length is extended to 2 21 cycles, regardless of the value of mod, which makes the quantization error spectrum look like broadband noise. this may degrade the inband phase noise at the pll output by as much as 10 db. for lowest noise, dither off is a better choice, particularly when the final loop bandwidth is low enough to attenuate even the lowest frequency fractional spur. integer boundary spurs another mechanism for fractional spur creation is the in t eractions between the rf vco frequency and the reference frequency. when these frequencies are not integer related (the point of a fractionaln synthesizer) spur sidebands appear on the vco output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the reference and the vco frequency. these spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth, hence the name integer boundary spurs. reference spurs reference spurs are generally not a problem in fractionaln sy n thesizers because the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechanism that bypasses the loop may cause a problem. feed through of low levels of onchip reference switching noise, through the rf in pin back to the vco, can result in reference spur levels as high as C90 dbc. pcb layout needs to ensure adequate isolation between vco traces and the input reference to avoid a possible feed through path on the board. spur consistency and fractional spur opti mization with dither off, the fractional spur pattern due to the qua ntization noise of the sdm also depends on the particular phase word with which the modulator is seeded. the phase word can be varied to optimize the fractional and subfractional spur levels on any particular frequency. thus, a lookup table of phase values corresponding to each frequency can be constructed for use when programming the ADF4150. if a lookup table is not used, keep the phase word at a constant value to ensure consistent spur levels on any particular frequency. phase resync the output of a fractionaln pll can settle to any one of the mo d phase offsets with respect to the input reference, where mod is the fractional modulus. the phase resync feature in the ADF4150 produces a consistent output phase offset with respect to the input reference. this is necessary in applications where the output phase and frequency are important, such as digital beam forming. see the phase programmability section for how to program a specific rf output phase when using phase resync. phase resync is enabled by setting bits [db16:db15] in register 3 to 1, 0. when phase resync is enabled, an internal timer generates sync signals at intervals of t sync given by the following formula: f po0l = lc,.45l.lacew oh4 f ft4 where: f ft4 is the pfd reference period.
ADF4150 preliminary technical data rev. pr i | page 22 of 27 clk_div_value is the decimal value programmed in bits [db14:db3] of register 3, and can be any integer in the range of 1 to 4095. mod is the modulus value programmed in bits [db14:db3] of register 1 (r1). when a new frequency is programmed, the second sync pulse after the le rising edge is used to resynchronize the output phase to the reference. the t sync time is to be programmed to a value that is as least as long as the worstcase lock time. this guarantees the phase resync occurs after the last cycle slip in the pll settling transient. in the example shown in figure 25, the pfd reference is 25 mhz and mod = 125 for a 200 khz channel spacing. t sync is set to 400 s by programming clk_div_value = 80. le phase frequency sync (internal) C100 0 100 200 1000 300 400 500 600 700 800 900 07325-020 time (s) pll settles to correct phase after resync t sync last cycle slip pll settles to incorrect phase figure 25. phase resync example phase programmability the phase word in register 1 controls the rf output phase,. as this word is swept from 0 to mod, the rf output phase sweeps over a 360 o range in steps of 360 o /mod.
preliminary technical data ADF4150 rev. pri | page 23 of 27 applications information direct conversion modulator direct conversion architectures are increasingly being used to imp lement base station transmitters. figure 26 shows how analog devices, inc. parts can be used to implement such a system. the circuit block diagram shows the ad9788 txdac? being used with the adl5375. the use of dual integrated dacs, such as the ad9788 with its specified 0.02 db and 0.004 db gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. the local oscillator(lo) is implemented using the ADF4150. the lowpass filter was designed using adisimpll for a channel spacing of 200 khz and a closedloop bandwidth of 35 khz. the lo ports of the ad5375 can be driven differentially from the complementary rf out a and rf out b outputs of the ADF4150. this gives better performance than a singleended lo driver and eliminates the use of a balun to convert from a singleended lo input to the more desirable differential lo inputs for the ad5375. the typical rms phase noise (100 hz to 5 mhz) of the lo in this configuration is 0.61 rms. the adl5375 accepts lo drive levels from ?10 dbm to 0 dbm. the optimum lo power can be software programmed on the ADF4150, which allows levels from ?4 dbm to +5 dbm from each output. the rf output is designed to drive a 50 ? load but must be ac c oupled, as shown in figure 26. if the i and q inputs are driven in quadrature by 2 v pp signals, the resulting output power from the modulator is approximately 2 dbm. ad9788 txdac refio fsadj modulated digital data qoutb iouta ioutb qouta 2k low-pass filter low-pass filter 2700pf 1200pf 39nf 680 360 v vco 3.9nh 3.9nh 1nf 1 n f spi compatible serial bus ADF4150 cp gnd agnd sd gnd r f in C rf in + rf o ut C r f out + c p 1nf 1nf 4.7k r set le data c lk ref in fref in dv dd av dd ce muxo ut 16 18 19 1 2 3 24 8 12 13 23 v dd lock dete ct 51 10 11 14 20 21 ld 9 7 pdb rf 17 6 22 sdv dd vp 5 sw 4 15 ibbp ibbn adl5375 rfou t loip l oin qbbn qbbp quadrature phase splitter dsop 51 51 51 51 vco 100pf 100pf v vco v tune v cc vco out av dd agnd figure 26 direct conversion modulator
ADF4150 preliminary technical data rev. pri | page 24 of 27 interfacing the ADF4150 family has a simple spi?compatible serial int erface for writing to the device. clk, data, and le control the data transfer. when le goes high, the 32 bits that have been clocked into the appropriate register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 5 for the register address table. aduc812 interface figure 27 shows the interface between the ADF4150 family and the aduc812 microconverter?. because the aduc812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the ADF4150 family needs a 32bit word, which is accomplished by writing four 8bit bytes from the microconverter to the device. when the fourth byte has been written, the le input should be brought high to complete the transfer. 07325-022 aduc812 ADF4150 clk sda ta le ce muxout (lock detect) sclock mosi i/o ports figure 27. aduc812 to ADF4150 interface i/o port lines on the aduc812 are also used to control power down (ce input) and detect lock (muxout configured as lock detect and polled by the port input). when operating in the described mode, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 125 khz. adsp-21xx interface figure 28 shows the interface between the ADF4150 family and the adsp21xx digital signal processor. the ADF4150 family needs a 32bit serial word for each latch write. the easiest way to accomplish this using the adsp21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. 07325-023 adsp-21xx ADF4150 clk sda ta le ce muxout (lock detect) sclock mosi tfs i/o ports figure 28. adsp-21xx to ADF4150 interface set up the word length for 8 bits and use four memory locations for each 32bit word. to program each 32bit latch, store the 8bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. pcb design guidelines for chip scale pack age the lands on the chip scale package (cp243) are rectangular. the pcb pad for these is to be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land is to be centered on the pad. this ensures the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the pcb is to be at least as large as the exposed pad. on the pcb, there is to be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, they are to be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter is to be between 0.3 mm and 0.33 mm, and the via barrel is to be plated with one ounce copper to plug the via.
preliminary technical data ADF4150 rev. pri | page 25 of 27 output matching there are a number of ways to match the output of the ADF4150 for optimum operation; the most basic is to use a 50 resistor to av dd . a dc bypass capacitor of 100 pf is connected in series as shown in figure 29. because the resistor is not frequency dependent, this provides a good broadband match. the output power in this circuit into a 50 load typically gives values chosen by bit d2 and bit d1 in register 4 (r4). 100pf 07325-021 rf out av dd 50 50 figure 29. simple ADF4150 output stage a better solution is to use a shunt inductor (acting as an rf choke) to av dd . this gives a better match and, therefore, more output power. experiments have shown the circuit shown in figure 30 provides an excellent match to 50 for the wcdma umts band 1 (2110 C 2170 mhz). the maximum output power in that case is about 7 dbm. both singleended architectures can be examined using the evalADF4150eb1z evaluation board. 3.9nh 1nf 07325-025 rf out av dd 50 figure 30.optimum ADF4150 output stage if differential outputs are not needed, the unused output can be terminated or combined with both outputs using a balun.
ADF4150 preliminary technical data rev. pri | page 26 of 27 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0 .18 compliant to jedec standards mo-220-wggd. 112108-a bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3 .90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic ator 1 24 7 12 13 18 19 6 2.65 2.50 sq 2.45 figure 31. 24-lead lead frame chip scale package [lfcsp_vq] dimensions shown in millimeters(package drawing subject to change). ordering guide model tem perature range package description package option ADF4150bcpz 1 ?40c to +85c 24-lead lead frame chip scale package [lfcsp_vq] cp-24-7 ADF4150bcpz-rl7 1 ?40c to +85c 24-lead lead frame chip scale package [lfcsp_vq] cp-24-7 eval-ADF4150eb1z 1 evaluation board 1 z = rohs compliant part.
preliminary technical data ADF4150 rev. pri | page 27 of 27 pr08226-0-4/09(pri) notes

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